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In PCB manufacturing, vias connect different layers of a circuit board. As electronic devices become more compact and complex, drilling and plating vias alone are no longer enough for stable performance. This is where via filling becomes essential, as it improves both the electrical reliability and the mechanical strength of the PCB. Widely used in HDI boards and advanced component packages like BGA and QFN, via filling has become a key technology in achieving miniaturisation, high performance, and durability.
This guide explores PCB via filling, including the definition, types, and manufacturing process of via fill. ELEPCB also provides design guidelines and solutions to common failures that lead to a more robust and high-yield fabrication.
What is PCB Via Filling?
A via is a tiny hole drilled into a printed circuit board (PCB) to create an electrical connection between different layers. In standard PCB designs, vias are typically hollow and plated with copper. Check out this blog post to learn more about vias: What is PCB Via? A Complete Guide!
Via filling refers to filling the holes with conductive or non-conductive materials. Conductive fillers such as silver epoxy or copper allow a path for current to flow through the vias and increase heat dissipation. Non-conductive fillers such as resin or epoxy add mechanical strength to the via structure, prevent solder from flowing into holes during assembly, and form a level surface for component mounting.
When to Use Via Filling in PCB Design
PCB Via fill is particularly advantageous in applications where signal integrity, thermal management, and reliability are paramount.
On high-density interconnect (HDI) boards with microvias or stacked vias, filling the vias mechanically reinforces the vias and ensures planarity during lamination or component mounting.
- Via filling is commonly applied in designs with vias in pads, such as under BGAs, QFNs, or CSPs. This wicks solder and provides a smooth pad surface for stable solder joints.
- For high-speed or high-frequency circuits, conductive-filled vias minimize impedance change and signal reflection. For power electronics and thermal pad designs, conductive filling increases the current-carrying capacity and thermal dissipation.
- When boards are exposed to humid or corrosive environments, filling seals the vias and improves their long-term reliability.
Note: If your layout has few vias and requires low power and low speed, and does not require being highly mechanically rugged, then a basic unfilled (or simply plated) via may suffice.
Via Filling vs. Via Plugging
It is important to distinguish between via filling and via plugging. While both involve covering or sealing vias, via plugging usually means closing the via partially with solder mask or resin, whereas via filling refers to completely filling the via barrel. Filled vias are often required in via-in-pad designs, especially under fine-pitch packages like BGAs, where a smooth and reliable pad surface is critical.
| Feature / Aspect | Via Filling | Via Plugging |
| Definition | The process of completely filling the via barrel with conductive or non-conductive material | The process of partially closing the via using solder mask or resin |
| Material Used | Conductive paste (e.g., silver epoxy, copper) or non-conductive resin/epoxy | Mainly solder mask ink or resin |
| Coverage | Fills the entire via hole (barrel) | Seals the via opening partially, not filling the entire hole |
| Surface Result | Creates a flat and solid pad surface, suitable for component mounting | Surface may still have a slight depression or bump |
| Application | Common in via-in-pad designs for BGA/QFN packages, HDI PCBs, and high-frequency boards | Used where vias need to be protected from contamination or solder leakage, but not necessarily flattened |
| Advantages | Improves reliability, prevents solder wicking, enhances thermal & electrical performance | Lower cost, simpler process, sufficient for less demanding applications |
| Best Use Case | High-density, fine-pitch designs requiring high reliability | Standard boards where cost efficiency is more important |
Types of Via Fillings
The PCB via filling material may be selected to maximize electrical conduction, thermal dissipation, or some kind of plugging; the objective of the filling process usually determines which of those criteria is desired.
The PCB via filling material may be selected to maximize electrical conduction, thermal dissipation, or some kind of plugging; the objective of the filling process usually determines which of those criteria is desired.
Conductive Epoxy Fill
A conductive epoxy fill consists of a special material made up of a polymer resin with metallic elements,resulting in copper filled vias or silver filled vias. This produces a hard-topped plug that serves both an electrical conduction and augmented warm conductivity between the barrel of the via. It is mainly utilized in via-in-pad, where it is critical in the creation of a solderable flat area over the via.
- An example of this is the use of conductive epoxy-filled vias that may be used to place a solder ball on a pad directly beneath a Ball Grid Array (BGA) component and efficiently dissipate heat away from the processor to keep the CPU cool and ensure secure electrical performance.
Non-conductive Epoxy Fill
Non-conductive epoxy fill is an insulating polymer paste to fill a via barrel fully, but to ensure no pathway is formed. It is mainly intended to be used to prevent catastrophic assembly failures, like solder wicking, where solder flows down a hole during reflow as a result of an empty hole, starving the surface joint and leaving it open. It is also useful to seal the hole to trap process chemicals or moisture that may later volatilize and cause delamination or “popcorning.”
- A typical application is to border the periphery of a large-scale BGA and fill the vias in areas that are not being fan-out, so solder is not at every joint where it is not needed, and thus reliability is compromised.
Soldermask Fill
Soldermask fill involves the use of Liquid Photo Imageable (LPI) soldermask material to fill the openings of via holes. This is a very cost-effective way of ensuring basic environmental protection and protecting the via against moisture and minimal contamination. But, since the spans chiefly extend across the opening in the form of a bridge, it most frequently leaves an air-space beneath and is not quite a perfectly flat surface. It is, therefore, inappropriate to use via-in-pad applications where planarity is of utmost importance in placing the component. Moreover, it also provides no heat conduction or strengthening.
- A traditional application is in low-cost consumer electronics, where vias are routed in non-critical areas where the flatness of the surface is not the top priority.
Comparison Table of Via Filling Methods
| Via Filling Method | Materials Used | Key Features | Advantages | Limitations / Considerations | Typical Applications |
| Soldermask Fill | Soldermask ink | Covers the via opening without fully filling the barrel | Low cost, easy to process, prevents contamination and solder bridging | Not a true fill (only covers), weak mechanical strength | Standard PCBs, low-density boards where reliability is not critical |
| Non-conductive Epoxy Fill | Epoxy resin, dielectric materials | Completely fills via with insulating material (no conductivity) | Provides mechanical reinforcement, prevents solder wicking, cost-effective | Does not conduct electricity, not suitable for thermal/current paths | Via-in-pad for BGA/QFN, HDI PCBs, mechanical strengthening |
| Conductive Epoxy Fill | Silver epoxy, conductive paste | Fills via with conductive material, allowing current flow and heat transfer | Enhances thermal dissipation and electrical reliability | Higher cost, risk of voids, requires precise processing | Power electronics, thermal vias, high-performance or high-current designs |
Advantages of Via Filling
Via filling provides a long list of benefits that are vital to the current PCB manufacturing and assembly process.
Enhanced Reliability
Eliminates the entrapment of air, moisture, or process chemicals during assembly (e.g., soldering, cleaning) that may form gases, corrosion, or delamination after assembly.
Better Thermal Management
Conductive epoxy fills can be used as thermal vias, where heat can be readily transferred away from high-power components such as CPUs and GPUs to heat sinks on the opposite side of the board.
Prevention of Solder Wicking
During surface-mount technology (SMT) assembly, a solder paste can wick down through a space in a via, starving the intended joint on the surface and leaving a solder defect. Via blocks this path off.
High-Density Design Support
Filled and capped vias support via-in-pad design, where vias are positioned directly in the component pad. This is required in routing fine-pitch Ball Grid Array (BGA) and chip-scale package (CSP) components.
Improved Via Planarity
The vias are filled and planarized to provide a planar surface, which is important so that components can be placed accurately on the vias. An unsmooth surface will cause tombstoning or a lack of solder connections.
Manufacturing Process of Filled Vias
Step 1: Drilling
Step 2: Cleaning and Desmear
Step 3: Electroless Copper Deposition
Through-holes are typical of high-speed, computer-controlled spindle drills with solid carbide drill bits. Lasers cut through material with accuracy to form clean tapered vias needed in HDI designs. The entry and backup boards are drilled to avoid burring and maintain the quality of clean holes. Both feed rate and spin speed of the drill bit are dynamically determined according to the stack-up material to eliminate as much thermal stress and drill smear as possible.
The holes are cleared of debris, and a chemical process is employed to remove resin smear in inner-layer copper pads. Plasma etchings are used on high-reliability and exotic substrates (or plasma desmear). An anisotropic etching of organic residue is performed by a reactive gas plasma (e.g., CF₄/O₂), which produces a cleaner and more microscopically rough surface that improves plating adhesion.
Electroless copper plating is used to deposit a thin primary layer of copper on the hole walls so they conduct electricity. The walls of the hole and the board receive a continuous conductive layer of copper (usually 0.5-1.0 µm) deposited through an autocatalytic chemical reduction process on the entire surface of the walls and board. This is accomplished without electricity.
Step 4: Electroplating
Step 5: Filling
Step 6: Curing
A thicker, more robust layer of copper is electroplated onto the hole walls to provide an assured electrical connection. The cathode is attached to the board, and the electrolytic bath contains copper and immerses the board. The copper is deposited on the whole panel surface and the walls of the via holes with a uniform thickness (25-40 µm or about 1 mil). This creates a solid, cylindrical, copper conductor in the via.
A special squeegee or vacuum apparatus is used to force a paste of non-conductive or conductive epoxy into the plated through-holes. Through-holes are plated with a specialized low-viscosity, high-thermogravimetric stability epoxy paste (conductive or non-conductive), which is mechanically forced into the plated holes. This is done through vacuum-assisted filling or through a sequential printing/squeegee procedure.
The board is placed in an oven in order to completely harden and fix the epoxy substance within the vias. The boards are taken through a controlled thermal cycle in a conveyorized oven. This step hardens the epoxy resin and evaporates the solvents, hardening the material completely so that it is no longer a paste, but a solid plug.
Step 7: Planarization
Step 8: Surface Plating
Any unnecessary cured epoxy that is on the surface would be smoothed down using mechanical grinding to give an altogether smooth finish. This is to be a surface which is parallel or nearly parallel to the copper substrate surrounding it, deviated less than 2 mils (0.05mm). This is a perfect planarity, which is obligatory for the effective placement of via-in-pad and fine-pitch parts.
An electrolytic copper (usually 15-25 µm) is plated over the whole surface. This deposits a new copper layer that smoothly overcoats the planarized via and becomes part of the surface circuitry that will later be imaged and etched.
Key Design Considerations for Via Fill
When designing using filling processes, it is crucial to consider a range of factors to ensure reliability, manufacturability and long-term performance. The following elements have a significant impact on the final outcome.
Optimize Aspect Ratio for Reliability
The quotient of the via depth and its diameter. A smaller aspect ratio (6:1 and below) will be simpler to fill because a gap will not be noticeable.
The ratio is 8:1, using a via drill diameter of 0.2mm, on a 1.6mm thick board, and that is a high-risk fill. Rather, a safer 5.3:1 ratio required is a 0.3mm drill. This is so that the epoxy material will flow all the way to the bottom, and there will be no voids that trap the chemicals, which will lead to reliability failure issues in the future.
Select the Proper Via Size for Easier Filling
When using filled vias, do not use the common 0.1mm mechanical drills to fill a dense 0.8mm thick wearable. The small hole is difficult to wash and seal. Use 0.15mm laser-drilled vias; the amount of these vias is smaller overall, but it is simpler to fill them to the brim without leaving a surface dimple after being planarized.
Choose a Suitable Fill Material for Better Performance
Select the fill material (conductive/non-conductive) depending on electrical/thermal requirements. In laying an IC that has thermal power via array, apply conductive epoxy paste to the thermal via array. This forms a continuous and solid plug, which forms a low-resistance conduit of heat transfer between components and down into the internal ground plane, which greatly enhances thermal conductivity and handling.
Ensure a Flat Surface in Via-in-Pad Designs
In the case of a BGA via-in-pad, the copper must be electroplated into the filled via to form an entirely smooth and flat surface. This is an important step in capping to ensure the solder paste does not wick into the via or fill up in a dimple during reflow and form a defective solder joint.
Failure Analysis of Filled Vias
Voids (Air Bubbles in Fill)
Voids are usually created when filling an insufficient or an overly high aspect ratio by trapping air.
The remedy is to maximize the filling process through applying vacuum filling, minimize the aspect ratio of the via in the design, and fill material with proper viscosity to guarantee full filling of the cavity.
Bad Surface Planarity
This is because the epoxy surface that serves as the base of the filling process is not planarized or, in other words, is not grounded after the curing process.
To fix this, it is necessary to use a PCB fabricator who has very accurate planarization hardware and to strictly control the planarization process, in addition to clearly indicating the necessary flatness (i.e., the planarization) of the surface on the fabrication drawings.
Electrical Failure
This critical error can be manifested by the use of a non-conductive epoxy unintentionally in a via that should have been electrically continuous between layers.
The answer is to accurately communicate and precisely examine the design intent to each of the via with the fabricator, clarifying any electrical and non-electrical fill.
Compliance and Quality: IPC Standards
For via filling, commonly used quality inspection standards include IPC-4761, IPC-6012, IPC-TM-650, and others.
- IPC-4761 categorizes filled (Type VI) vias and capped (Type VII) vias using the protection type.
- Acceptance criteria, including maximum permissible void tolerance and necessary surface planarity, are established in IPC-6012 to ensure acceptable performance.
- The compliance is checked in compliance with the IPC-TM-650 tests in cross-sectional analysis.
Conclusion
Via filling is a PCB fabrication process that is intricate and essential, and plays a significant role in the resolution of the problem of high-density electronics. It also dramatically increases board reliability, allows miniaturization with via-in-pad layouts, and has higher thermal management. The key to success lies in the careful choice of materials, a tightly managed production process, and a careful design that prevents the usual traps such as voids or even planarity.
At ELEPCB, we combine advanced vacuum via filling technology with strict adherence to IPC standards to deliver flawless results. If you are looking for a reliable partner to maximize the advantages of via filling and ensure long-term PCB performance, contact our experts today to discuss your project.
FAQ
A1: Aesthetic symptoms are such things as solder balls around the via following reflow, visible dimples or holes in the via cap, or an indented look on the solder pad. These are signs of outgassing of the fill.
A2: BGA pads may contain unfilled vias that lead to solder wicking, which causes an unreliable or broken connection. Filled vias may not be well-planned such that a ball does not come in proper contact; this is known as a head-in-pillow defect.
A3: Designs with aspect ratio vias, very large vias, or high densities of vias in a small area exacerbate this difficulty into a complete, void-free fill and pose a greater risk of planarity problems.
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