What are PCI and PCIe?
Concept of PCI
PCI (Peripheral Component Interconnect) is a local parallel bus standard originally designed to connect central processing units (CPUs) to external devices, introduced by Intel in 1991, PCI was developed by the PCI-SIG in the United States.
The most authoritative information about the PCI standard is the PCI Spec file issued by this organisation. You can try to search for the PCI Spec file for reading if you are interested. It has been updated to PCIe 7.0 version0.5.
The Configuration Process of the PCIce
The process generally includes:
- Addressing of the PCI
- Configuration space：wherein a PCI device has three addressing spaces
- IO ports
- Device memory
| PCIe Configuration | Aspect | Details |
| PCI Addressing | – | Addressing of the PCI – configuration space is part of the process. General Inclusion: It generally includes this addressing aspect. |
| PCI Device Addressing Spaces | Number | A PCI device has three addressing spaces. |
| PCI Device Addressing Spaces | Space Types | The types are IO ports and device memory. |
| PCI System Layout | System Startup | Access and registers of the PCI configuration space include system startup, during which the firmware PCI peripherals make configuration transactions. |
| PCI System Layout | Transactions | During system startup, configuration transactions exist between the firmware and the PCI peripherals. |
| PCI System Layout | I/O Registers | – I/O registers have a side effect. – They should not be cached by the CPU. |
| PCI Data Structures | – | pci_dev, pci_device_id, pci_driver, pci_register_driver, pci_unregister_driver, pci_enable_device |
| More Information Source | – | Check the PCI-SIG official website. |
The Development of PCI (PCI Or PCIe?)
Since 1992, the PCI interface has undergone major revamps to meet the ever-growing needs of computing. PCIe moved to a serial point-to-point architecture, thus increasing transfer rates and flexibility in systems.
- PCI 1.0: This is the first version, which allows for an operational frequency of 33 MHz and bandwidth of 133 MB/s.
- PCI 2.0: Introduction of the 66 MHz operating frequency, doubled bandwidth to 264 MB/s.
- PCI-X: IBM, HP and Compaq were responsible for introducing the next phase of this technology, namely PCI-X, which achieved further performance improvements by having 64-bit widths and frequencies up to 133 MHz.
| Time | Version | rate of data signalling |
| 2003 | PCIe 1.0 | 2.5 Gbps |
| 2007 | PCIe 2.0 | 5.0 Gbps |
| 2010 | PCIe 3.0 | 8.0 Gbps |
| 2017 | PCIe 4.0 | 16.0 Gbps |
| … | … | … |
| 2024-2025 | PCIe 7.0 | 512 GB/s（The two – way total bandwidth，based on the PCIe 7.0 x16 configuration） |
PCI in PCB Layout Design
Why is PCI Layout Necessary?
The PCI interface layout directly influences the performance and stability of the system; thus, the layout of a PCI interface is one of the most important issues in the design of a PCB.
Before going forward with the layout of this interface, two things should be well determined in advance:
- Determine the maximum data rate of the PCI interface.
(see above Table 2 The Development of PCIe)
- Define the coding scheme used by the PCI interface.
The PCI interface coding scheme has implications on a plethora of techniques including but not limited to advanced signaling, data integrity, transmit-receive equalization, PLL enhancement, time-varying data recovery, and general-purpose scaling.
| PCI Version | Coding system | GT/s | MB/s | More Info |
| PCI 1.0 | 8b/10b | – | – | Initial version, parallel bus |
| PCI 2.0 | 8b/10b | – | – | Increase bandwidth, maintain the original code |
| PCI 3.0 | 8b/10b | – | – | Added support for higher rates |
| PCI Express 1.0 (PCIe 1.0) | 8b/10b | 2.5 | 250 | Serial communication for the first time |
| PCI Express 2.0 (PCIe 2.0) | 8b/10b | 5 | 500 | transmission rate X 2 |
| PCI Express 3.0 (PCIe 3.0) | 128b/130b | 8 | 985 | Increased coding efficiency and doubled bandwidth |
| PCI Express 4.0 (PCIe 4.0) | 128b/130b | 16 | 1970 | Further increase bandwidth |
| PCI Express 5.0 (PCIe 5.0) | 128b/130b | 32 | 3940 | Seepd X 2 |
| PCI Express 6.0 (PCIe 6.0) | PAM4 | 64 | 7880 | The coding changes and the speed doubles again |
Steps of PCI Layout Design
Step 1: Locating the Slots
The physical layout of the interface of the PCI would start by locating the slots.
Ideally, these should be as close as possible to the location of the controller of the PCI on the motherboard for reducing the transmission path of the signal. Such a layout does not only reduce signal attenuation but also reduces the risk of EMI.
In practice, since there is area limitation and other component layout requirements, an ideal situation is sometimes hard to achieve, so the designer needs to lay them out in context.
The most essential elements for the PCI interface are differential pairs of signal lines.
Following are a few principles in wiring:
- Length Control : Length of the alignment from the edge of the gold finger to the PCI-E Switch pin must not be more than 4 inches, approximately 100 mm. This will limit the length in order to minimize signal attenuation and distortion.
- Differential Pair Spacing: Spacing of differential pairs shall be maintained even. Commonly, it is about 7 mils. Such even spacing maintains signal balance and reduces crosstalk.
- Length Matching: No more than a 5 mil length difference between any two traces in the same pair. Precise length matching is required in order to keep signal integrity, especially at high transmission speeds.
- Snaking: When length matching is required, snaking can be done. In this method, accurate matching is achieved with an increased length of the cable. But the size of the snake should be under control so that it may not affect signal quality.
Besides, special 25/14 hole design for PCI-E differential pairs, and the two holes must be symmetrically designed. This really helps to reduce distortion and reflection in the signals significantly.
Step 2: Ground Level Design
While designing the ground plane for a PCB’s PCI interface, several design factors should be considered by the designer, which may include but are not limited to the following:
- Signal integrity
- Power distribution
- Thermal management
- EMI protection
In the area of the PCI interface, it should be considered to arrange as much ground vias as possible. It is usually recommended that a few places in the BGA area add the ground via, and the differential signals are processed to wrap the ground.
The spacing of the ground holes should be less than 300 mil. These ground vias not only help in forming effective shielding but also significantly improve the quality of the signal.
Specific Design Case
The following data are only approximate references, and the actual design should be based on strict electrical specifications and testing requirements to determine the exact parameters.
Below is a brief list, for more specific details, please consult ELE‘s team of professional engineers.<Check This>
| Parameters | PCI-E 5.0(For Reference Only) |
| Trace impedance | 85 – 100 Ω |
| Maximum delay difference within differential pair | ＜0.1 ps/mm |
| Equal – length requirements between differential pairs | ＜5 mil (approx.0.127 mm) |
| Trace length | Determined according to specific design |
| Capacitance requirements | Determined according to specific design |
| Spacing between differential pairs | 8-10 mil (approx. 0.2 – 0,254 mm) |
| Maximum delay difference within differential pair (RefCLK) | ＜0.005 ps/mm |
| Trace impedance (RefCLK) | 90 – 95 Ω |
| Spacing between PCL – E and other signals | At least 15 mil (approx. 0.381 mm) |
| The number of vias allowed for each signal | A maximun of 3 per differential pair |
Pay attention to signal and power integrity
I. Signal Integrity
- Impedance Matching
- For high-speed PCI interfaces, the impedance is usually 50Ω. The line width tolerance needs to be controlled within 5 – 10%.
- Crosstalk Control
- Spacing Rule: The signal line spacing follows the “5W rule” (the spacing is 5 times the line width).
- Utilize differential pairs: Differential pair signal lines have natural crosstalk cancellation properties and are especially suitable for high-speed signal transmission.
- Layer Structure: Placing the signal layer between the power and ground layers can reduce crosstalk.
- Other Points
- Keeping the signal line close to the reference plane can improve signal quality.
- The length difference of differential pairs is usually controlled within 5 mils.
- Special 25/14 via design and symmetrical placement can reduce signal distortion and reflection.
II. Power Integrity
- Decoupling Capacitor Placement
- A 0.1μF high frequency decoupling capacitor is placed near the power pins (VCC18GND, VCC33GND) of the PCIe chip. The closer, the better it is to reduce the high frequency noise of the power supply.
- Power Plane Design
- Number of Layers: Typical PCIe boards use a 4 or 6 layer stack (two layers for signals and two layers for power).
- Bias: Set the power layer bias according to device requirements. Alternating signal and power layers can reduce crosstalk and EMI.
- Via Design
- Use large vias, double vias, and dual-circuit power supplies to reduce voltage drop and improve stability.
PCI & PCIe Applications
PCB Server Motherboard
High Integration Density
- Server motherboards require several PCIe slots for the expansion of different devices.
Redundancy and Reliability
- Supporting hot-swap during operation
- Using error detection & correction
- Employing redundant configuration, such as dual power.
Support PCIe 4.0+
- To overcome the problem of signal attenuation and noise.
Thermal Management
- Good thermal design for stability with high-performance PCIe devices like a GPU.
PCB Industrial Control Board
Anti-interference Design
- High-density shielded connectors avoid interference.
- Vertical insertion of the adapter card contributes to good ventilation, lowering interference.
- Anti-jamming on data acquisition cards improved with 5000 V rms isolation.
Reliability Design
- Low-power CPUs, such as Pentium MMX-266, with heat sink for high-temp resistance.
- DiskOnChip electronic disk for anti-vibration.
- Hot swap, redundant power for high availability.
- Hot swappable adapter cards for easy maintenance.
PCB Embedded System Board
Simplified PCI Protocol
- Implement simplified protocol stack in FPGA
- For example, basic bus commands.
State Machine Optimisation
- Simplification of state machines for better use of resources and faster response.
Power Consumption Optimization
- Use intelligent power management
- For example, idle (low-power) states-for extending the battery life.
Modularity:
- Divide the PCI interface into separate modules.
- For instance, address decoders.
Performance Metrics You May Care About
In the PCI interface PCB design, customers are most concerned about the performance indicators mainly include bandwidth, latency and power consumption; compatibility, service life, cost is also an important indicator.
Bandwidth
Bandwidth is the basic measure of the transfer capability of a PCI interface. However, in real-world applications, there are various factors that effective bandwidth always makes compromise.
For example, assuming the overhead of 8b/10b encoding, the actual effective bandwidth in a system working on PCIe 3.0 is about 80% of the original bandwidth.
Besides, there are TLP Overhead, Ack/Nak mechanisms, and Flow Control that may affect the actual effective bandwidth.
| Version | Bandwidth |
| PCIe 3.0 | 8 GT/s |
| PCIe 4.0 | 16 GT/s |
| PCIe 5.0 | 32 GT/s |
Latency
New features introduced-like the PAM-4 multilevel channel technology of PCIe 5.0-while increasing bandwidth, unfortunately also introduce other signal integrity challenges capable of increased latency creation.
Power Consumption
- The other factor that is not negligible in designing the PCI interfaces, in particular for mobile devices and for embedded systems, is power consumption.
- On this second aspect, the PCIe 6.0 standard improves a lot by using new, advanced power states such as L0p that dynamically adjusts power consumption according to bandwidth requirements.
- Besides these three key metrics, other performance parameters that customers may care about include IOPS, queue depth and error rates.
Compatibility
Slot Compatibility
- PCIe x16 slots can support smaller-form-factor PCIe cards like PCIe x8, PCIe x4, and PCIe x1.
Protocol Compatibility
- Newer PCIe protocol versions come with new features while still being backward compatible with earlier generations.
Power Compatibility
- Newer PCIe slots are able to supply appropriate power to older-generation PCIe cards.
Compatibility Limitations
Power Management Challenges
- High-performance PCIe 4.0 or 5.0 devices may require enhanced power management systems, which could be impossible on older platforms.
Feature Implementation
- As the PCIe standard has evolved, some of the newer features, such as the L0s low-power state in PCIe 4.0, are not implemented on older devices, thus impacting the overall energy efficiency of the system.
Reliability and Lifespan
To ensure the long-term reliability of your PCI interface, you need to look at a number of areas, including material selection, thermal management, signal integrity, and more.
Cost
There are a number of factors that can affect the cost of manufacturing a PCI, and I’ll show some of them briefly here:
Conclusion
PCI in a PCB is complex yet an essential feature in pcb manufacturing. The conventional PCI or the PCIe evolved finds extensive usage in a PCB design. A well-laid-out PCI interface with due consideration to signal and power integrity is the basis for superior performance. The implementation of PCI varies in different types of PCBs; hence, the designers must know the relevant performance metrics. Proper PCI design stands at the basis of ensuring good data transfer and smooth functioning of various components in a system.
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