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Design Rule Check (DRC) is a common verification process used in the creation of electrical design and printed circuit board manufacturing. It verifies that a PCB layout is compliant with DRC rules that were defined in order to avoid manufacturing defects and to improve circuit reliability.
What are DRC rules, and real-world case studies of importance of DRC rules will be discussed in this article. ELEPCB will show you how to follow it flexibly in this blog.
PCB Design Rule Check Flowchart
How to Follow the DRC Rule
to Gain Maximum Advantages as an Engineer?
Senior engineers know that the real worth of a DRC test is not mechanically passing an inspection but applying the rules to arrive at the optimum solution for performance, cost, and manufacturability. So before the inspection, the first thing we must do is not a brain to ship the PCB to the inspection, but the first PCB product positioning.
To give a simple example, for consumer electronics motherboards, if it is consumer electronics motherboard, our primary goal is naturally to take into account the cost, how to target the final cost-effective bottom to ensure the quality, and then before the test, my preparation beforehand is how to set the limit of line width that might be achieved by the manufacturer; and if for military radar board, we don’t mind at all compromising the cost of reliability of the board, then what is most precious to be careful about should be the control over the redundancy of the spacing as well as resisting resistance.
| Type | Cost weights | Performance weights | Reliability weights |
| consumer electronics motherboard | 5/5 | 4/5 | 3/5 |
| military radar board | 3/5 | 4/5 | 5/5 |
The second thing that must be taken into account in advance is the rules document process capability table (e.g., laser drilling minimum aperture, copper thickness tolerance range) and special process guidelines (e.g., HDI board staggered hole limitations) and other important PCB manufacturing data.
In addition, you must ascertain some of the blinders, i.e., some of the PCB makers note “6mil line width” is actually referring to the outer layer of the line, the inner layer can accept 5mil, these have to be cleared in advance. You may also list a table or color-code non-negotiable requirements and negotiable requirements passed to your manufacturer.
How DRC Prevents Manufacturing Defects?
Making sure a PCB layout fits manufacturing constraints is one of the goals of DRC. Some of the issues that can occur due to violations of DRC rules include:
- Signal integrity problems
- Component misalignment
DRC Rules You must Obey
Electrical Safety Creepage Distance
As regards the creepage distance for electrical safety, the following requirements have to be implemented:
- In the case of the 12V power module, according to the IPC-2221 standard, the creepage distance has to be ≥0.5mm.
- For the 220V AC input, considering the needs of the UL certification, the creepage distance has to be ≥3.2mm.
Hints for Copper-Laying Areas
In copper-laying areas, the “trenching” technology needs to be adopted instead of full isolation to achieve maximum heat dissipation and safety space.
Soldermask Bridge Control
For QFN packages, the solder mask bridge between pins should ≥3mil, which can avoid the short circuiting of solder beads.
Safety Regulation Marking
- According to CE certification requirements, the high voltage areas should be printed with the ⚡ mark and have a 2mm isolation zone.
- For medical devices, critical signal paths should be silkscreened with a “Do Not Cross” label.
Drilled Hole-to-Pad Ratio
- For through-hole devices, the pad size during the manufacturing process should ≥ drilled hole size +8mil (1mil = 0.0254mm), which can prevent broken holes.
- For blind holes, bottom pad size of blind holes should ≥ the size of the drilled hole + 4mil.
PCB DRC Rules Tips You may Need
Considerations for High-Speed/High-Frequency Designs
- Differential Pair Length MatchingTolerance: 5% of total length or 0.1mm per segment (whichever is smaller).Compensation Strategy: Serpentine routing should prioritize low-coupling regions (e.g., away from vias or power planes) for length adjustment.
- Reference Plane Integrity
Design Compromises in Space-Constrained Check Layouts
Silkscreen Override Rules
BGA Area Exemption:
- Silkscreen may temporarily cover BGA pads (requires post-manual removal).
- Critical parameters (e.g., pin 1 marking) must be labeled with 0.8mm mini-font.
Keep-out Zone Optimization
Board-edge Mounting Holes:
Default 5mm keep-out can be reduced to 2mm when:
- Countersunk screws are employed.
- No high-speed signals exist in adjacent layers.
Cost-Driven Design Rules
- Via Treatment GuidelinesBatch Production (>10k units):
- Full solder mask coverage on vias to prevent SMT defects.
Prototype/Small Batch:- Windowed vias allowed to reduce solder mask alignment costs.
- Panelization EfficiencyV-Cut Tolerance: ±0.2mm positional error permitted.Staggered Array Layout:
- Increases utilization to 92% while maintaining structural integrity.
Strategies for Software DRC Functions
Altium Designer Best Practices
Rule Priority Hierarchy:
- Differential Pair Spacing: 6 mil.
- Power Plane Copper Connections: Minimum 15 mil width (based on current-carrying capacity calculations).
- Silkscreen-to-Pad Clearance: 4 mil (to avoid solder mask encroachment).
Area-Specific Rule Implementation:
- DDR4 Routing Zone: Enforce 3W rule (trace center-to-center spacing ≥ 3× trace width).
- General Signal Zones: Maintain default 2W rule.
Critical Defect Detection
RF Module Exemptions:
- Permanently exclude floating copper in antenna regions from DRC checks.
- Annotate non-standard thermal pad-to-mechanical hole connections as “Design Intent”.
Physical Interference Detection:
- Identify component collisions missed by DRC (e.g., electrolytic capacitor body-to-envelope spacing < 0.5 mm).
- Support STEP model integration with CTE (Coefficient of Thermal Expansion) compensation analysis.
Automated Methods
Script-Based Batch Processing (Tcl Example)
foreach pad [get_pads -of_objects [get_cell]] {
if {[get_property $pad LAYER] == "BOTTOM"} {
set_property SOLDERMASK_EXPANSION $pad 0.1mm
}
}
| Level | Color | Action Required | Examples |
| Critical | Red | Mandatory Fix | Clearance violation (< 4 mil) |
| Advisory | Yellow | Recommended | Discontinuous reference plane |
| Info | Green | Acceptable | Silkscreen overlap for labeling |
DRC Group Strategies
- Pre-Production Verification Group: Disabled checks irrelevant to fab capabilities (e.g., non-standard drill aspect ratios).
- High-Speed Design Group: Include impedance tolerance (±10%) and return path integrity checks.
Case Study: Tesla Model 3 Controller PCB Thermal Via Failure
Tesla Model 3s were recalled in 2020 for thermal via cracks on the controller PCB through high-temperature cycling. The root cause of failure was a lack of crucial manufacturing constraints within the DRC rule library that led to design flaws reaching the production stage [2].
Why Fail?
- Critical Defect: 2 mil thermal via-to-anti-pad gap violated manufacturer process limits (IPC-7093D requires ≥4 mil [1]).
- Detection Blindspot: The rule was left out of DRC checks, and therefore is not accessible to standard SI/PI analysis workflows.
- Test Protocol: JESD22-A104 [4] compliant temperature cycling (-40℃↔125℃ at 1 cycle/hour).
- Failure Mode: Complete annular ring cracks observed after 200 cycles (Fig.1), with very high concentration at layer 4-6 transitions [2].
Solutions
1. Set a Hierarchical DRC Rule (Lisp)
;; Rule 1: Critical Signal Definition (Per Intel Agilex 7 FPGA Requirements [3])
(rule "Critical_Signals"
;; Condition: Applies to PCIe5 or USB4 net classes
(condition "NetClass == 'PCIe5' || NetClass == 'USB4'")
;; Constraint 1: Minimum trace width 4.5mm (for 20A current carrying)
(constraint min_width 4.5mm)
;; Constraint 2: Minimum clearance 4.5mm (crosstalk suppression)
(constraint clearance 4.5mm)
)
Validation Method:
- Current capacity calculated by IPC-2221 equations [1], validated with PCB Toolkit [5] (ΔT ≤15℃ @25℃ ambient).
- 3D field solver simulations for DDR4 signals (impedance tolerance ±7%).
2. Reliability Enhancement
Structural Optimization: Employed “teardrop + cross-shaped connection” via arrays to minimize CTE mismatch stress.
Process Compensation: Increased copper weight to 2oz for >3A paths with Ansys Icepak thermal validation.
Conclusion
Design Rule Check is an important process in PCB design to ensure that the designed PCBs follow the industry standards and manufacturing limitations. Using strict DRC rules, designers can catch defects, avoid electrical inefficiencies, and improve product reliability. An effective DRC design rule check process saves time, cuts costs, and helps ensure a seamless transition from design to production.
References
-
IPC, Design and Reliability of High-Density PCBs, IPC-7093D, 2017.
-
NHTSA, Tesla Model 3 Recall Report, 2020. [Online]. Available: https://www.nhtsa.gov/vehicle/2020/TESLA/MODEL%2525203/4%252520DR/RWD#recalls
-
Intel, Agilex 7 FPGA PCB Design Guidelines, 2023. [Online]. Available: https://www.intel.com/content/www/us/en/docs/programmable/683864/current/pcb-design-guidelines.html
-
JEDEC, Thermal Cycling Test Standard, JESD22-A104, 2020.
-
A. Brooks, PCB Toolkit: Current Capacity Calculator, 2024. [Online]. Available: https://saturnpcb.com/saturn-pcb-toolkit/
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